Publication:

The CMOS 2.0 revolution

Date

2024
Editorial Material
https://doi.org/10.1038/s44287-023-00016-3
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cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.orcid#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.orcid0009-0001-4359-2478
cris.virtualsource.departmented894ec9-d595-4dd3-943b-8d99244a104d
cris.virtualsource.department90d64a2b-bf15-4151-aa98-0461ad5e3b50
cris.virtualsource.orcided894ec9-d595-4dd3-943b-8d99244a104d
cris.virtualsource.orcid90d64a2b-bf15-4151-aa98-0461ad5e3b50
dc.contributor.authorRyckaert, Julien
dc.contributor.authorSamavedam, Sri
dc.date.accessioned2026-06-15T14:13:20Z
dc.date.available2026-06-15T14:13:20Z
dc.date.createdwos2025-12-04
dc.date.issued2024
dc.description.abstractA general-purpose framework and continuous miniaturization have been key to the success of CMOS technology. However, the recent explosion in compute requirements across a growing variety of architectures and applications is happening at a time when CMOS technology faces unprecedented scaling and cost challenges. This requires reimagining of the existing paradigm.
dc.identifier.doi10.1038/s44287-023-00016-3
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/59718
dc.language.isoeng
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherSPRINGERNATURE
dc.source.beginpage139
dc.source.endpage140
dc.source.issue3
dc.source.journalNATURE REVIEWS ELECTRICAL ENGINEERING
dc.source.numberofpages2
dc.source.volume1
dc.title

The CMOS 2.0 revolution

dc.typeEditorial material
dspace.entity.typePublication
imec.internal.crawledAt2026-04-07
imec.internal.sourcecrawler
imec.internal.wosCreatedAt2026-04-07
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