Publication:
Multi-node scaling potential of monolithic CFET
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| dc.contributor.author | Yang, Sheng | |
| dc.contributor.author | Verschueren, Lynn | |
| dc.contributor.author | Boemmels, Juergen | |
| dc.contributor.author | Kükner, Halil | |
| dc.contributor.author | Lin, Ji-Yung | |
| dc.contributor.author | Bufler, Fabian | |
| dc.contributor.author | Sankatali, Venkateswarlu | |
| dc.contributor.author | Farokhnejad, Anita | |
| dc.contributor.author | Van de Put, Maarten | |
| dc.contributor.author | Hellings, Geert | |
| dc.date.accessioned | 2026-07-23T08:25:29Z | |
| dc.date.available | 2026-07-23T08:25:29Z | |
| dc.date.createdwos | 2026 | |
| dc.date.issued | 2025 | |
| dc.description.abstract | This paper explores design strategies and Power-Performance-Area (PPA) trade-offs for scaling monolithic Complementary FETs (CFETs) from the A7 to A3 technology nodes. At A7 node, we demonstrate gate and Middle-of-Line (MOL) parasitic capacitance optimization to match N2 node performance. At A5 node, an Omega-gate Forksheet (O-FS) architecture keeps performance at the same level at lower sheet width. At A3 node, asymmetric crystal orientation engineering enhances drive current and supports aggressive area scaling targets. | |
| dc.description.wosFundingText | This work has been enabled in part by the NanoIC pilot line. The acquisition and operation are jointly funded by the Chips Joint Undertaking, through the European Union's Digital Europe (101183266) and Horizon Europe programs (101183277), as well as by the participating states Belgium (Flanders), France, Germany, Finland, Ireland and Romania. For more information, visit nanoic-project.eu. | |
| dc.identifier.doi | 10.1109/iedm50572.2025.11353555 | |
| dc.identifier.isbn | 979-8-3315-6786-6 | |
| dc.identifier.issn | 2380-9248 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/59909 | |
| dc.language.iso | eng | |
| dc.provenance.editstepuser | greet.vanhoof@imec.be | |
| dc.publisher | IEEE | |
| dc.source.conference | IEEE International Electron Devices Meeting (IEDM) | |
| dc.source.conferencedate | 2025-12-06 | |
| dc.source.conferencelocation | San Francisco | |
| dc.source.journal | 2025 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, IEDM | |
| dc.source.numberofpages | 4 | |
| dc.title | Multi-node scaling potential of monolithic CFET | |
| dc.type | Proceedings paper | |
| dspace.entity.type | Publication | |
| imec.internal.crawledAt | 2026-07-14 | |
| imec.internal.source | crawler | |
| imec.internal.wosCreatedAt | 2026-07-14 | |
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