Junction-engineered Scaled High-performance GAA Nanosheet FETs with Ultra-low Temperature (< 350 °C) SiGe:B Source/Drain

Abstract

We present an ultra-low-temperature (ULT) boron-doped SiGe (SiGe:B) epitaxial (epi) layer as PMOS junction in a gate-all-around (GAA) Si nanosheet (NS) transistor at 48 nm contacted poly-pitch (CPP) and 14 nm gate length (LG). We investigate the impact of dopant concentration and diffusion on NS performance at different RTA conditions. We find that the ULT junction (with S/D epi growth temperature <350 °C) with controlled RTA (at 800°C) delivers over 100% improvement in performance (ID,LIN and gm,LIN) over our reference process of record (POR) epitaxy process (at 500°C) by significantly increasing the active dopant concentration and carefully position the junction under the inner spacer without degrading the short-channel effects (SCE). Moreover, contact resistivity (ρc) reduces by ~3.5x compared to reference POR epi process.