Publication:
Via resistance optimization at advanced sub-2nm nodes
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.orcid | 0000-0002-1058-9424 | |
| cris.virtual.orcid | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.orcid | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.orcid | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.orcid | 0000-0003-3545-3424 | |
| cris.virtualsource.department | d41bbdfd-20df-46cf-9106-e8e19a469a8d | |
| cris.virtualsource.department | 66017fdc-05d4-4021-a802-f1ff7b4721d3 | |
| cris.virtualsource.department | 61f92014-61e2-404b-ae56-3f0501c0fa70 | |
| cris.virtualsource.department | 3b94c016-2e7f-4dc8-9787-1f526d5665b1 | |
| cris.virtualsource.department | 5345513e-14d5-47e9-a494-1dda4ed18864 | |
| cris.virtualsource.orcid | d41bbdfd-20df-46cf-9106-e8e19a469a8d | |
| cris.virtualsource.orcid | 66017fdc-05d4-4021-a802-f1ff7b4721d3 | |
| cris.virtualsource.orcid | 61f92014-61e2-404b-ae56-3f0501c0fa70 | |
| cris.virtualsource.orcid | 3b94c016-2e7f-4dc8-9787-1f526d5665b1 | |
| cris.virtualsource.orcid | 5345513e-14d5-47e9-a494-1dda4ed18864 | |
| dc.contributor.author | Soussou, Assawer | |
| dc.contributor.author | Marti, Giulio | |
| dc.contributor.author | Tokei, Zsolt | |
| dc.contributor.author | Park, Seongho | |
| dc.contributor.author | Vincent, Benjamin | |
| dc.date.accessioned | 2026-04-23T10:01:07Z | |
| dc.date.available | 2026-04-23T10:01:07Z | |
| dc.date.createdwos | 2025-10-18 | |
| dc.date.issued | 2025 | |
| dc.description.abstract | In this work, via resistance of Ru versus Cu at a 22nm metal pitch (MP) was explored and benchmarked using semi damascene (SD) and dual damascene (DD) patterning schemes. Via resistance variability was analyzed and compared using multiple process options during process modeling. The impact of process variations and patterning sensitivities on via resistance was also investigated. This process sensitivity simulation allowed us to identify the lowest via resistance options for sub-2nm technology nodes. | |
| dc.identifier.doi | 10.1109/IITC66087.2025.11075464 | |
| dc.identifier.isbn | 979-8-3315-3782-1 | |
| dc.identifier.issn | 2380-632X | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/59178 | |
| dc.language.iso | eng | |
| dc.provenance.editstepuser | greet.vanhoof@imec.be | |
| dc.publisher | IEEE | |
| dc.source.conference | IEEE International Interconnect Technology Conference (IITC) | |
| dc.source.conferencedate | 2025-06-02 | |
| dc.source.conferencelocation | Busan | |
| dc.source.journal | 2025 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, IITC | |
| dc.source.numberofpages | 3 | |
| dc.title | Via resistance optimization at advanced sub-2nm nodes | |
| dc.type | Proceedings paper | |
| dspace.entity.type | Publication | |
| imec.internal.crawledAt | 2025-10-22 | |
| imec.internal.source | crawler | |
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