Publication:

Virtual Process-Based Spacer & Junction Optimization for an Inverter Circuit

Date

2020
Proceedings Paper
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dc.contributor.authorGuissi, S.
dc.contributor.authorMeijer, P.
dc.contributor.authorSchram, Tom
dc.contributor.authorSchuddinck, Pieter
dc.contributor.authorDemuynck, Steven
dc.contributor.imecauthorSchram, T.
dc.contributor.imecauthorSchuddinck, P.
dc.contributor.imecauthorDemuynck, S.
dc.contributor.imecauthorSchram, Tom
dc.contributor.imecauthorSchuddinck, Pieter
dc.contributor.imecauthorDemuynck, Steven
dc.contributor.orcidimecSchram, Tom::0000-0003-1533-7055
dc.date.accessioned2021-11-22T11:13:24Z
dc.date.available2021-11-02T16:05:56Z
dc.date.available2021-11-22T11:13:24Z
dc.date.issued2020
dc.identifier.eisbn978-1-7281-2539-8
dc.identifier.issnna
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/38243
dc.publisherIEEE
dc.source.conferenceIEEE Electron Devices Technology and Manufacturing Conference (EDTM)
dc.source.conferencedateMAR 16-18, 2020
dc.source.conferencelocationPenang, Malaysia
dc.source.journalna
dc.source.numberofpages4
dc.title

Virtual Process-Based Spacer & Junction Optimization for an Inverter Circuit

dc.typeProceedings paper
dspace.entity.typePublication
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