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Power efficient architecture for high-speed decoding of block turbo-codes with the Fang-Buda algorithm

Date

2002
Proceedings Paper
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dc.contributor.authorRullmann, M.
dc.contributor.authorBougard, Bruno
dc.contributor.authorBrockmeyer, Erik
dc.contributor.authorGiulietti, A.
dc.contributor.authorCatthoor, Francky
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.date.accessioned2021-10-14T22:59:40Z
dc.date.available2021-10-14T22:59:40Z
dc.date.embargo9999-12-31
dc.date.issued2002
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/6778
dc.source.beginpage252
dc.source.conferenceIEEE Workshop on Signal Processing Systems - SIPS
dc.source.conferencedate16/10/2002
dc.source.conferencelocationSan Diego, CA USA
dc.source.endpage257
dc.title

Power efficient architecture for high-speed decoding of block turbo-codes with the Fang-Buda algorithm

dc.typeProceedings paper
dspace.entity.typePublication
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