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Optimisation of a thin epitaxial Si layer as Ge passivation layer to demonstrate deep sub-micron n- and p-FETs on Ge-On-Insulator substrates

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dc.contributor.authorDe Jaeger, Brice
dc.contributor.authorBonzom, Renaud
dc.contributor.authorLeys, Frederik
dc.contributor.authorRichard, Olivier
dc.contributor.authorVan Steenbergen, Jan
dc.contributor.authorWinderickx, Gillis
dc.contributor.authorVan Moorhem, Els
dc.contributor.authorRaskin, G.
dc.contributor.authorLetertre, F.
dc.contributor.authorBillon, T.
dc.contributor.authorMeuris, Marc
dc.contributor.authorHeyns, Marc
dc.contributor.imecauthorDe Jaeger, Brice
dc.contributor.imecauthorRichard, Olivier
dc.contributor.imecauthorVan Steenbergen, Jan
dc.contributor.imecauthorWinderickx, Gillis
dc.contributor.imecauthorVan Moorhem, Els
dc.contributor.imecauthorMeuris, Marc
dc.contributor.imecauthorHeyns, Marc
dc.contributor.orcidimecDe Jaeger, Brice::0000-0001-8804-7556
dc.contributor.orcidimecRichard, Olivier::0000-0002-3994-8021
dc.contributor.orcidimecMeuris, Marc::0000-0002-9580-6810
dc.date.accessioned2021-10-16T01:08:04Z
dc.date.available2021-10-16T01:08:04Z
dc.date.issued2005-06
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/10299
dc.source.beginpage26
dc.source.endpage29
dc.source.journalMicroelectronic Engineering
dc.source.volume80
dc.title

Optimisation of a thin epitaxial Si layer as Ge passivation layer to demonstrate deep sub-micron n- and p-FETs on Ge-On-Insulator substrates

dc.typeJournal article
dspace.entity.typePublication
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