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Three-Dimensional Modeling of BEOL TDDB: Variability Specs for Sub-20 nm Half-Pitch Interconnects

 
dc.contributor.authorFang, Yu
dc.contributor.authorCiofi, Ivan
dc.contributor.authorRoussel, Philippe
dc.contributor.authorLesniewska, Alicja
dc.contributor.authorBlanco, Victor
dc.contributor.authorDegraeve, Robin
dc.contributor.authorWolf, I. De
dc.contributor.authorCroes, Kristof
dc.contributor.imecauthorCiofi, I.
dc.contributor.imecauthorRoussel, Ph. J.
dc.contributor.imecauthorLesniewska, A.
dc.contributor.imecauthorCarballo, V. M. Blanco
dc.contributor.imecauthorDegraeve, R.
dc.contributor.imecauthorCroes, K.
dc.date.accessioned2025-05-01T06:24:42Z
dc.date.available2025-05-01T06:24:42Z
dc.date.issued2025
dc.description.abstractA pragmatic 2-step model of back-end-of-line (BEOL) time-dependent dielectric breakdown (TDDB) is proposed, which accounts for the complex 3-D features in BEOL interconnects. First, for each point in the dielectric, the metal-to-metal shortest straight percolation path (SSPP) is extracted and the related failure probability is computed. Finally, weakest-link statistics are applied to predict the reliability of the investigated interconnect scheme. This model is fit to TDDB measurements from low-k planar capacitors with different thickness to capture the dependence of the model parameters on the SSPP length. This model is applied to generate variability specs for meeting ten years lifetime at operating conditions for sub-20 nm half-pitch interconnects. As for variability sources, via misalignment (VM), tip-to-tip spacing variation, line-edge roughness (LER), and die-to-die spacing variation are considered. It is predicted that nominal line-to-line spacings of 7 nm can be reliable when extreme ultraviolet lithography (EUV) spacer-assisted multi patterning is used as a litho-patterning process. Moreover, this model shows that fully self-aligned via (FSAV) processes can enable nominal line-to-line spacings as small as 5 nm, as they can prevent via-to-line failures.
dc.description.wosFundingTextThis work was supported by imec.
dc.identifier.doi10.1109/TED.2025.3554474
dc.identifier.issn0018-9383
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/45574
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.source.beginpage2165
dc.source.endpage2172
dc.source.issue5
dc.source.journalIEEE TRANSACTIONS ON ELECTRON DEVICES
dc.source.numberofpages8
dc.source.volume72
dc.subject.keywordsCHALLENGES
dc.title

Three-Dimensional Modeling of BEOL TDDB: Variability Specs for Sub-20 nm Half-Pitch Interconnects

dc.typeJournal article
dspace.entity.typePublication
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