Publication:

Linking Room- and Low-Temperature Electrical Performance of MOS Gate Stacks for Cryogenic Applications

Date

2022
Journal article
https://doi.org/10.1109/LED.2022.3162368
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dc.contributor.authorKao, K-H
dc.contributor.authorGodfrin, Clement
dc.contributor.authorElsayed, Asser
dc.contributor.authorLi, Roy
dc.contributor.authorSimoen, Eddy
dc.contributor.authorGrill, Alexander
dc.contributor.authorKubicek, Stefan
dc.contributor.authorRadu, Iuliana
dc.contributor.authorGovoreanu, Bogdan
dc.contributor.imecauthorGodfrin, Clement
dc.contributor.imecauthorElsayed, Asser
dc.contributor.imecauthorLi, Roy
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.imecauthorGrill, Alexander
dc.contributor.imecauthorKubicek, Stefan
dc.contributor.imecauthorRadu, Iuliana
dc.contributor.imecauthorGovoreanu, Bogdan
dc.contributor.orcidimecGodfrin, Clement::0000-0002-5244-3474
dc.contributor.orcidimecLi, Roy::0000-0002-2145-7590
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.contributor.orcidimecGrill, Alexander::0000-0003-1615-1033
dc.contributor.orcidimecRadu, Iuliana::0000-0002-7230-7218
dc.contributor.orcidimecElsayed, Asser::0000-0002-5264-5682
dc.contributor.orcidimecGovoreanu, Bogdan::0000-0001-7210-2979
dc.contributor.orcidimecKubicek, Stefan::0009-0006-2163-5760
dc.date.accessioned2022-09-01T13:09:23Z
dc.date.available2022-05-23T02:19:32Z
dc.date.available2022-09-01T13:09:23Z
dc.date.embargo2022-05-31
dc.date.issued2022
dc.description.wosFundingTextThis work was supported in part by imec through the Quantum Computing imec Industrial Affiliation Program (IIAP) and in part by the European Union's Horizon 2020 Research and Innovation Program under Agreement 951852 (QLSI). The work of K.-H. Kao was supported by the Ministry of Science and Technology, Taiwan, under Grant MOST 111-2636-E-006-023 and Grant 110-2218-E-006030-MBK. The review of this letter was arranged by Editor K. J. Kuhn.
dc.identifier.doi10.1109/LED.2022.3162368
dc.identifier.issn0741-3106
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/39884
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.source.beginpage674
dc.source.endpage677
dc.source.issue5
dc.source.journalIEEE ELECTRON DEVICE LETTERS
dc.source.numberofpages4
dc.source.volume43
dc.subject.keywordsFREQUENCY NOISE ASSESSMENT
dc.subject.keywordsOXIDE TRAP DENSITY
dc.subject.keywordsINTERFACE
dc.title

Linking Room- and Low-Temperature Electrical Performance of MOS Gate Stacks for Cryogenic Applications

dc.typeJournal article
dspace.entity.typePublication
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