Understanding Gate Breakdown Mechanisms in RF GaN MIS-HEMTs with thin gate SiN

Abstract

We investigate forward-biased gate breakdown mechanisms in RF GaN MIS-HEMTs employing thin in-situ MOCVD SiN gate dielectrics with thicknesses of 10, 3.5, and 1 nm. A refined ramped-voltage-stress (RVS) methodology is proposed, in which incremental gate-bias steps are combined with intermediate IG−VG checks to detect SiN degradation, overcoming the limitations of conventional constant-current breakdown criteria for ultra-thin dielectrics. We show that, depending on the dominant forward gate-leakage mechanism, SiN breakdown occurs at different equivalent electric fields. Time-dependent dielectric breakdown (TDDB) under constant-voltage stress (CVS) is further evaluated for the 10 nm (M10) and 3.5 nm (M3.5) stacks, enabling lifetime extrapolation and assessment against GaN power-amplifier (PA) operational requirements. The 10 nm SiN stack satisfies a 10-year PA reliability target, while thinner dielectrics fall short. Finally, by comparing forward and reverse CVS through combined measurement and device simulation, we demonstrate that high electric field alone is insufficient to trigger breakdown; instead, SiN failure is governed by the combined impact of electric field and injected charge. These results provide a comprehensive framework for gate-stack design and reliability qualification of thin-dielectric GaN MIS-HEMTs for RF PA applications.