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A low-power multi-gate FET CMOS technology with 13.9ps inverter delay, large-scale integrated high performance digital circuits and SRAM
Publication:
A low-power multi-gate FET CMOS technology with 13.9ps inverter delay, large-scale integrated high performance digital circuits and SRAM
Date
2007
Proceedings Paper
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
von Arnim, Klaus
;
Augendre, Emmanuel
;
Pacha, C.
;
Schulz, Thomas
;
San, Kemal Tamer
;
Bauer, F.
;
Nackaerts, Axel
;
Rooyackers, Rita
;
Vandeweyer, Tom
;
Degroote, Bart
;
Collaert, Nadine
;
Dixit, Abhisek
;
Singanamalla, Raghunath
;
Xiong, W.
;
Marshall, A.
;
Cleavelin, C.R.
;
Schrüfer, K.
;
Jurczak, Gosia
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1988
since deposited on 2021-10-16
Acq. date: 2025-10-23
Citations
Metrics
Views
1988
since deposited on 2021-10-16
Acq. date: 2025-10-23
Citations