Through-silicon via etch uniformity enhancement and aspect-ratio influence on etch rate and profile

Abstract

High-aspect ratio (HAR) through-silicon via (TSV) etching is a critical process for three-dimensional interconnect (3Di) integration, requiring strict within-wafer (WiW) depth uniformity and profile stability. In this study, we systematically investigated TSV profile and WiW uniformity by varying process parameters in a conventional inductively coupled plasma (ICP) etch system, without employing hardware level uniformity control. A stable baseline process was initially established for TSVs with a critical dimension of 5 μm at an aspect ratio (AR) of 10, achieving uniform etch depth and straight via profiles with vertical sidewalls across the wafer. Using this baseline as a reference, the impact of increasing AR was examined. As the etch depth increased, the measured average etch rate exhibited an exponential decrease, indicating increasingly pronounced transport limitations. At AR 15, competing requirements for entrance profile stability and effective bottom etching became evident, leading to a clear trade-off depending on process optimization strategy. At higher AR 20, severe profile degradation and wafer-level nonuniformity emerged, including pronounced bowing, tapering, and localized etch-stop behavior near the wafer edge. These results provide experimental insight into the limitations of parameter-only optimization in standard ICP etch chambers under extreme HAR conditions.