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3D resist profile evolution in high-NA EUV lithography for random logic vias: simulation and experiment insights

 
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cris.virtual.orcid0000-0002-8297-5076
cris.virtual.orcid0000-0003-4308-0381
cris.virtual.orcid0000-0001-7668-2480
cris.virtual.orcid0009-0000-3384-8540
cris.virtualsource.departmentbf23291b-8cd7-495b-b210-564de11c9d4f
cris.virtualsource.department88d4cdb2-8ec4-4aa4-87ee-9719850d7416
cris.virtualsource.department45d53b1a-0445-4cce-8499-827e157195ef
cris.virtualsource.department39ffd6c3-9161-4c05-9b59-66e46fdee6b8
cris.virtualsource.orcidbf23291b-8cd7-495b-b210-564de11c9d4f
cris.virtualsource.orcid88d4cdb2-8ec4-4aa4-87ee-9719850d7416
cris.virtualsource.orcid45d53b1a-0445-4cce-8499-827e157195ef
cris.virtualsource.orcid39ffd6c3-9161-4c05-9b59-66e46fdee6b8
dc.contributor.authorChowrira Poovanna, Bhavishya
dc.contributor.authorDe Bisschop, Peter
dc.contributor.authorBlanco, Victor
dc.contributor.authorDusa, Mircea
dc.date.accessioned2026-09-17T13:53:43Z
dc.date.available2026-09-17T13:53:43Z
dc.date.createdwos2026
dc.date.issued2026
dc.description.abstractHigh numerical aperture (high-NA) extreme ultraviolet lithography (EUVL) introduces challenges in resist profile control and pattern fidelity, particularly for advanced logic via configurations. We evaluate resist profile evolution and local critical dimension uniformity (LCDU) across different via configurations under 0.55 NA extreme ultraviolet exposure. We integrate aerial image modelling with a physics-based resist development framework and benchmark simulated profiles against wafer inspection data, including after-development and after-etch stages. At best focus, all tested via configurations (isolated, doublet, and diagonal triplet) exhibit LCDU below 2 nm, whereas positive defocus causes significant LCDU degradation in the dense diagonal triplet pattern, indicating strong layout-dependent focus sensitivity. Importantly, conventional top-down critical dimension (CD) scanning electron microscopy metrology is found to overestimate the lithographic process window by failing to capture incomplete resist openings and bottom CD loss observable in cross-section. These results underscore the need for detailed three-dimensional resist profile analysis and integrated lithography–etch co-optimization to ensure robust process development at high-NA EUVL.
dc.description.wosFundingTextThis work has been enabled in part by the NanoIC pilot line. The acquisition and operation are jointly funded by the Chips Joint Undertaking, through the European Union's Digital Europe (Grant No. 101183266) and the Horizon Europe Programs (Grant No. 101183277), as well as by the participating states Belgium (Flanders), France, Germany, Finland, Ireland, and Romania. For more information, visit https://www.nanoic-project.eu.
dc.identifier.doi10.1117/1.jmm.25.2.021202
dc.identifier.eissn2708-8340
dc.identifier.issn1932-5150
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/60415
dc.language.isoeng
dc.provenance.editstepusermeghan.oneill@imec.be
dc.publisherSPIE-SOC PHOTO-OPTICAL INSTRUMENTATION ENGINEERS
dc.relation.ispartofseriesJournal of Micro/Nanopatterning, Materials, and Metrology
dc.source.beginpage021202
dc.source.issue2
dc.source.journalJOURNAL OF MICRO-NANOPATTERNING MATERIALS AND METROLOGY-JM3
dc.source.numberofpages7
dc.source.volume25
dc.title

3D resist profile evolution in high-NA EUV lithography for random logic vias: simulation and experiment insights

dc.typeJournal article
dspace.entity.typePublication
imec.internal.crawledAt2026-04-07
imec.internal.sourcecrawler
imec.internal.wosCreatedAt2026-09-07
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