Enabling metrology and inspection for CFET structures using hybrid qualification approaches

Abstract

Complementary field-effect transistor (CFET) integration increases metrology and inspection complexity by combining vertically stacked device tiers, multilayer high-aspect-ratio (HAR) pattern transfer, coupled 3D recess geometries, waferto-wafer (W2W) bonding interfaces, and backside processing. This work presents a hybrid qualification methodology that integrates high-throughput inspection, targeted high-resolution review, and model-based parameter extraction to support process-window qualification (PWQ) and in-line monitoring. For HAR gate patterning, broadband optical inspection with deep-learning (DL) classification and electron-beam (e-beam) review enables defect-type-aware PWQ within highly sampled care areas, while high-precision SEM metrology is applied to isolate stochastic line-edge roughness (LER) components. For vertical control, SEM backscattered-electron (BSE) indices provide a scalable proxy for trench depth under stated monotonic-response assumptions. For 3D recess modules, multi-channel optical geometry extraction tracks global fin/cavity parameters and is validated against cross-sectional references, while micro-spot X-ray fluorescence (µXRF) provides model-free, material-sensitive SiGe recess depth monitoring on dense device patterns. For bonding, high-frequency scanning acoustic microscopy (SAM) detects buried-interface voids at sub-µm pattern resolution. Finally, e-beam inspection evaluates source/drain uniformity, while voltage-contrast e-beam inspection screens backside metal-to-source/drain connectivity, correlating with electrical test signatures.