Publication:

Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus

 
dc.contributor.authorPei, Zhenlin
dc.contributor.authorLiu, Hsiao-Hsuan
dc.contributor.authorMayahinia, Mahta
dc.contributor.authorTahoori, Mehdi B.
dc.contributor.authorCatthoor, Francky
dc.contributor.authorTokei, Zsolt
dc.contributor.authorAbdi, Dawit
dc.contributor.authorMyers, James
dc.contributor.authorPan, Chenyun
dc.contributor.imecauthorLiu, Hsiao-Hsuan
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.imecauthorTokei, Zsolt
dc.contributor.imecauthorAbdi, Dawit
dc.contributor.imecauthorMyers, James
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.contributor.orcidimecTokei, Zsolt::0000-0003-3545-3424
dc.contributor.orcidimecAbdi, Dawit::0000-0002-3598-8798
dc.date.accessioned2024-10-09T07:35:08Z
dc.date.available2024-09-04T17:46:25Z
dc.date.available2024-10-09T07:35:08Z
dc.date.issued2024
dc.description.wosFundingTextThis work was supported in part by the Inter university Microelectronics Centre (IMEC), in part by the Advanced Scientific Computing Research(ASCR) Program of U.S. Department of Energy (DOE) under Award DE-SC0022881, and in part by the National Science Foundation (NSF) under Grant CCF-2219753.
dc.identifier.doi10.1109/TCSI.2024.3438164
dc.identifier.issn1549-8328
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/44403
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.source.beginpage4597
dc.source.endpage4610
dc.source.issue10
dc.source.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
dc.source.numberofpages14
dc.source.volume71
dc.subject.keywordsCO-OPTIMIZATION
dc.subject.keywordsTECHNOLOGY
dc.subject.keywordsCACHE
dc.subject.keywordsCU
dc.title

Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus

dc.typeJournal article
dspace.entity.typePublication
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