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Adaptive Hardware Architecture for Neural-Network-on-Chip

 
dc.contributor.authorKhalil, Kasem
dc.contributor.authorDey, Bappaditya
dc.contributor.authorKumar, Ashok
dc.contributor.authorBayoumi, Magdy
dc.contributor.imecauthorDey, Bappaditya
dc.contributor.orcidimecDey, Bappaditya::0000-0002-0886-137X
dc.date.accessioned2022-12-21T10:55:53Z
dc.date.available2022-10-14T02:52:50Z
dc.date.available2022-10-18T09:55:13Z
dc.date.available2022-12-21T10:55:53Z
dc.date.issued2022
dc.identifier.doi10.1109/MWSCAS54063.2022.9859323
dc.identifier.eisbn978-1-6654-0279-8
dc.identifier.isbn978-1-6654-0279-8
dc.identifier.issn1558-3899
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/40568
dc.publisherIEEE
dc.source.conferenceIEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS)
dc.source.conferencedateAUG 07-10, 2022
dc.source.conferencelocationFukuoka
dc.source.journalna
dc.source.numberofpages4
dc.subject.disciplineElectrical & electronic engineering
dc.title

Adaptive Hardware Architecture for Neural-Network-on-Chip

dc.typeProceedings paper
dspace.entity.typePublication
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