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A Study of Microbump Metrology and Defectivity at 20 Micron Pitch and Below for 3D TSV Stacking

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cris.virtual.orcid0000-0001-7048-2242
cris.virtual.orcid0009-0001-2277-3958
cris.virtual.orcid0000-0002-3096-050X
cris.virtual.orcid0000-0003-3000-7193
cris.virtualsource.departmente5c0246a-be78-4d4a-9b20-a32ec1475090
cris.virtualsource.department396b9467-2161-4a7a-bb47-9db73e169cd2
cris.virtualsource.department67066e7b-3582-42ef-b040-694dc2e501ae
cris.virtualsource.department83b6679c-4eda-4eb1-832e-d690c3e31a34
cris.virtualsource.orcide5c0246a-be78-4d4a-9b20-a32ec1475090
cris.virtualsource.orcid396b9467-2161-4a7a-bb47-9db73e169cd2
cris.virtualsource.orcid67066e7b-3582-42ef-b040-694dc2e501ae
cris.virtualsource.orcid83b6679c-4eda-4eb1-832e-d690c3e31a34
dc.contributor.authorHaensel, Leander
dc.contributor.authorLiebens, Maarten
dc.contributor.authorVandeweyer, Tom
dc.contributor.authorMiller, Andy
dc.contributor.authorBeyne, Eric
dc.contributor.authorWiesiollek, Markus
dc.contributor.authorEisenbach, Heiko
dc.contributor.authorFilzen, Marc
dc.contributor.authorWen, Youxian
dc.contributor.authorSood, Sumant
dc.date.accessioned2026-10-29T13:28:22Z
dc.date.available2026-10-29T13:28:22Z
dc.date.issued2015
dc.description.abstractABSTRACT As 3D TSV technology and 3D stacking moves into pre-production phase, the characterization of many of the different critical modules within the TSV middle integration flows becomes more and more crucial. Microbump dimensions are being scaled down to microbump pitch of 20 micron where the microbumps are 10 micron in width and 8 micron in height. This is required in order to achieve higher interconnect densities. For die-to-die and die-to-wafer stacking, the need for highly accurate and repeatable measurement of microbumps at both die-level and wafer-level is an absolute must for this technology to become a viable industrial option. For process development, maximum possible number of bumps needs to be characterized while for process monitoring, a meaningful subset of bumps per die and dies per wafer have to be qualified. In this paper we show the fundamental requirement for defectivity (damaged or missing bumps) and metrology to be done simultaneously for complete 3D microbump characterization. Additionally we discuss the challenges of measuring 3D microbumps in terms of CD (Critical Dimension), bump height, die-level bump coplanarity, bump shape and finally the repeatability of those measurements. Microbumps have been measured both pre and post bump reflow at a wafer- and die-level, with a statistical evaluation of measurement accuracy and repeatability. The data shown is primarily concerning 20 micron bump pitch with additional data showing early 10 micron bump pitch activity. Finally we show the differences in requirements for short loop measurement capability vs fully processed wafers, discussing the challenges introduced by multiple metal layer patterning on pattern recognition and feature recognition. We also perform an early assessment of the increase difficulty of moving from 20 micron bump pitch to 10 micron bump pitch on full flow wafers, examining the uncertainty in measurement alignment and accuracy caused by the increased background imagery.
dc.identifier.doi10.37665/wafgkwh82752
dc.identifier.issn3067-9052
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/60659
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherSMTA
dc.source.conference12th Wafer-Level Packaging Symposium
dc.source.conferencedate2015-10-13
dc.source.conferencelocationSan Jose
dc.source.journal12th Wafer-Level Packaging Symposium
dc.title

A Study of Microbump Metrology and Defectivity at 20 Micron Pitch and Below for 3D TSV Stacking

dc.typeProceedings paper
dspace.entity.typePublication
imec.internal.crawledAt2025-12-02
imec.internal.sourcecrawler
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