Publication:

Wafer-to-Wafer Hybrid Bonding Technology with 300nm Interconnect Pitch

Date

2025
Proceedings Paper
https://doi.org/10.1109/ECTC51687.2025.00100
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dc.contributor.authorVan Huylenbroeck, Stefaan
dc.contributor.authorChew, Soon Aik
dc.contributor.authorZhang, Boyao
dc.contributor.authorBogaerts, Lieve
dc.contributor.authorHeyvaert, Cindy
dc.contributor.authorDewilde, Sven
dc.contributor.authorIacovo, Serena
dc.contributor.authorStucchi, Michele
dc.contributor.authorDe Vos, Joeri
dc.contributor.authorBeyer, Gerald
dc.contributor.authorBeyne, Eric
dc.date.accessioned2026-03-24T14:21:33Z
dc.date.available2026-03-24T14:21:33Z
dc.date.createdwos2025-10-31
dc.date.issued2025
dc.description.abstractA wafer to wafer hybrid bonding technology is realized featuring a hybrid interconnect pitch scaling down to 300 nm. Integration challenges and optimizations are extensively discussed. High electrical yield on large daisy chain structures is demonstrated.
dc.identifier.doi10.1109/ECTC51687.2025.00100
dc.identifier.isbn979-8-3315-3933-7
dc.identifier.issn0569-5503
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/58938
dc.language.isoeng
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherIEEE COMPUTER SOC
dc.source.beginpage554
dc.source.conferenceIEEE 75th Electronic Components and Technology Conference (ECTC)
dc.source.conferencedate2025-03-27
dc.source.conferencelocationDallas
dc.source.endpage558
dc.source.journal2025 IEEE 75TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, ECTC
dc.source.numberofpages5
dc.title

Wafer-to-Wafer Hybrid Bonding Technology with 300nm Interconnect Pitch

dc.typeProceedings paper
dspace.entity.typePublication
imec.internal.crawledAt2025-10-22
imec.internal.sourcecrawler
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