Publication:
A smaller, faster and more energy-efficient complementary STT-MRAM cell uses three transistors and a ground grid: more is actually less
Date
| dc.contributor.author | Appeltans, Raf | |
| dc.contributor.author | Raghavan, Praveen | |
| dc.contributor.author | Kar, Gouri Sankar | |
| dc.contributor.author | Furnemont, Arnaud | |
| dc.contributor.author | Van der Perre, Liesbet | |
| dc.contributor.author | Dehaene, Wim | |
| dc.contributor.imecauthor | Appeltans, Raf | |
| dc.contributor.imecauthor | Kar, Gouri Sankar | |
| dc.contributor.imecauthor | Furnemont, Arnaud | |
| dc.contributor.imecauthor | Dehaene, Wim | |
| dc.contributor.orcidimec | Furnemont, Arnaud::0000-0002-6378-1030 | |
| dc.date.accessioned | 2021-10-24T02:52:46Z | |
| dc.date.available | 2021-10-24T02:52:46Z | |
| dc.date.issued | 2017 | |
| dc.identifier.issn | 1063-8210 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/27757 | |
| dc.identifier.url | http://ieeexplore.ieee.org/document/7779145/ | |
| dc.source.beginpage | 1204 | |
| dc.source.endpage | 1214 | |
| dc.source.issue | 4 | |
| dc.source.journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | |
| dc.source.volume | 25 | |
| dc.title | A smaller, faster and more energy-efficient complementary STT-MRAM cell uses three transistors and a ground grid: more is actually less | |
| dc.type | Journal article | |
| dspace.entity.type | Publication | |
| Files | ||
| Publication available in collections: |