This letter presents the physical design exploration of a domain-specific instruction-set processor (DSIP) architecture targeted at machine learning (ML), addressing the challenges of interconnect efficiency in advanced Angstrom-era technologies. The design emphasizes reduced wire length and high core density by utilizing specialized memory structures and single-instruction, multiple-data (SIMD) units. Five configurations are synthesized and evaluated using IMEC’s A10 nanosheet node. Key physical design metrics are compared across configurations and against VWR2A, a state-of-the-art (SoA) DSIP baseline. Results show that our architecture achieves over two times lower normalized wire length and more than three times higher density than the SoA, with low variability in the metrics across all configurations, making it a promising solution for next-generation DSIP designs. These improvements are achieved with minimal manual layout intervention, demonstrating the architecture’s intrinsic physical efficiency and potential for low-cost wire-friendly implementation.
