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Reduction of circuit complexity by elimination of internal nodes in the circuit modeling of planar interconnection structures

Date

1995
Proceedings Paper
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dc.contributor.authorCoen, G.
dc.contributor.authorDe Zutter, Daniel
dc.contributor.imecauthorDe Zutter, Daniel
dc.date.accessioned2021-09-29T13:04:38Z
dc.date.available2021-09-29T13:04:38Z
dc.date.issued1995
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/564
dc.source.beginpage229
dc.source.conferenceElectrical Performance of Electronic Packaging; 2-4 Oct. 1995; Portland, OR, USA.
dc.source.conferencelocation
dc.source.endpage231
dc.title

Reduction of circuit complexity by elimination of internal nodes in the circuit modeling of planar interconnection structures

dc.typeProceedings paper
dspace.entity.typePublication
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