Publication:

Exploration of segmented bus as scalable global interconnect for neuromorphic computing

Date

2019
Proceedings Paper
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dc.contributor.authorBalaji, Adarsha
dc.contributor.authorWu, Yuefeng
dc.contributor.authorDas, Anup
dc.contributor.authorCatthoor, Francky
dc.contributor.authorSchaafsma, Siebren
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.imecauthorSchaafsma, Siebren
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.date.accessioned2021-10-27T07:28:49Z
dc.date.available2021-10-27T07:28:49Z
dc.date.issued2019
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/32482
dc.identifier.urlhttps://doi.org/10.1145/3299874.3319491
dc.source.conferenceGLSVLSI '19: Proceedings of the 2019 on Great Lakes Symposium on VLSI
dc.source.conferencedate1/05/2019
dc.source.conferencelocationTysons Corner, VA USA
dc.title

Exploration of segmented bus as scalable global interconnect for neuromorphic computing

dc.typeProceedings paper
dspace.entity.typePublication
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