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Impact of Sub-µm Wafer Thinning on Latch-Up Risk in DTCO/STCO Scaling Era

 
dc.contributor.authorSerbulova, Kateryna
dc.contributor.authorChen, Shih-Hung
dc.contributor.authorHellings, Geert
dc.contributor.authorVeloso, Anabela
dc.contributor.authorJourdain, Anne
dc.contributor.authorDe Boeck, Jo
dc.contributor.authorGroeseneken, Guido
dc.contributor.imecauthorSerbulova, Kateryna
dc.contributor.imecauthorChen, Shih-Hung
dc.contributor.imecauthorHellings, Geert
dc.contributor.imecauthorVeloso, Anabela
dc.contributor.imecauthorJourdain, Anne
dc.contributor.imecauthorGroeseneken, Guido
dc.contributor.imecauthorDe Boeck, Jo
dc.contributor.orcidimecSerbulova, Kateryna::0000-0001-7326-9949
dc.contributor.orcidimecChen, Shih-Hung::0000-0002-6481-2951
dc.contributor.orcidimecHellings, Geert::0000-0002-5376-2119
dc.contributor.orcidimecJourdain, Anne::0000-0002-7610-0513
dc.contributor.orcidimecGroeseneken, Guido::0000-0003-3763-2098
dc.contributor.orcidimecDe Boeck, Jo::0000-0001-8244-1552
dc.date.accessioned2024-09-25T10:05:07Z
dc.date.available2024-03-25T17:22:01Z
dc.date.available2024-09-25T10:05:07Z
dc.date.issued2024
dc.identifier.doi10.1109/TED.2024.3367315
dc.identifier.issn0018-9383
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/43728
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.source.beginpage2278
dc.source.endpage2283
dc.source.issue4
dc.source.journalIEEE TRANSACTIONS ON ELECTRON DEVICES
dc.source.numberofpages6
dc.source.volume71
dc.title

Impact of Sub-µm Wafer Thinning on Latch-Up Risk in DTCO/STCO Scaling Era

dc.typeJournal article
dspace.entity.typePublication
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