Publication:
A 65fJ/conversion-step, 0-to-50MS/s 0-to-0.7mW 9bit charge-sharing SAR ADC in 90nm digital CMOS
Date
| dc.contributor.author | Craninckx, Jan | |
| dc.contributor.author | Van der Plas, Geert | |
| dc.contributor.imecauthor | Craninckx, Jan | |
| dc.contributor.imecauthor | Van der Plas, Geert | |
| dc.contributor.orcidimec | Craninckx, Jan::0000-0002-3980-0203 | |
| dc.contributor.orcidimec | Van der Plas, Geert::0000-0002-4975-6672 | |
| dc.date.accessioned | 2021-10-16T15:25:51Z | |
| dc.date.available | 2021-10-16T15:25:51Z | |
| dc.date.issued | 2007-02 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/11921 | |
| dc.source.beginpage | 246 | |
| dc.source.conference | International Solid-State Circuits Conference - ISSCC | |
| dc.source.conferencedate | 11/02/2007 | |
| dc.source.conferencelocation | San Francisco, CA USA | |
| dc.source.endpage | 247 | |
| dc.title | A 65fJ/conversion-step, 0-to-50MS/s 0-to-0.7mW 9bit charge-sharing SAR ADC in 90nm digital CMOS | |
| dc.type | Proceedings paper | |
| dspace.entity.type | Publication | |
| Files | ||
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