Publication:

A novel low-voltage biasing scheme for double gate FBC achieving 5s retention and 10^16 endurance at 85°C

Date

2010
Proceedings Paper
Simple item page Full metadata Statistics
 
dc.contributor.authorLu, Zhichao
dc.contributor.authorCollaert, Nadine
dc.contributor.authorAoulaiche, Marc
dc.contributor.authorDe Wachter, Bart
dc.contributor.authorDe Keersgieter, An
dc.contributor.authorSchwarzenbach, W.
dc.contributor.authorBonnin, O.
dc.contributor.authorBourdelle, K.K.
dc.contributor.authorNguyen, B.-Y.
dc.contributor.authorMazure, C.
dc.contributor.authorAltimime, Laith
dc.contributor.authorJurczak, Gosia
dc.contributor.imecauthorCollaert, Nadine
dc.contributor.imecauthorDe Wachter, Bart
dc.contributor.imecauthorDe Keersgieter, An
dc.contributor.imecauthorJurczak, Gosia
dc.contributor.orcidimecCollaert, Nadine::0000-0002-8062-3165
dc.contributor.orcidimecDe Keersgieter, An::0000-0002-5527-8582
dc.date.accessioned2021-10-18T18:33:28Z
dc.date.available2021-10-18T18:33:28Z
dc.date.embargo9999-12-31
dc.date.issued2010
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/17537
dc.source.beginpage288
dc.source.conferenceIEEE International Elecrton Devices Meeting - IEDM
dc.source.conferencedate6/12/2010
dc.source.conferencelocationSan Francisco, CA USA
dc.source.endpage291
dc.title

A novel low-voltage biasing scheme for double gate FBC achieving 5s retention and 10^16 endurance at 85°C

dc.typeProceedings paper
dspace.entity.typePublication
Files

Original bundle

Name:
20805.pdf
Size:
590.8 KB
Format:
Adobe Portable Document Format
Download
Publication available in collections:
Conference contributions