A DfT architecture and tool flow for 3D-SICs with test data compression, embedded cores, and multiple towers

dc.contributor.author	Papameletis, Christos
dc.contributor.author	Keller, Brion
dc.contributor.author	Chickermane, Vivek
dc.contributor.author	Hamdioui, Said
dc.contributor.author	Marinissen, Erik Jan
dc.contributor.imecauthor	Marinissen, Erik Jan
dc.contributor.orcidimec	Marinissen, Erik Jan::0000-0002-5058-8303
dc.date.accessioned	2021-10-22T21:39:28Z
dc.date.available	2021-10-22T21:39:28Z
dc.date.embargo	9999-12-31
dc.date.issued	2015
dc.identifier.issn	2168-2355
dc.identifier.uri	https://imec-publications.be/handle/20.500.12860/25734
dc.identifier.url	http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7089208
dc.source.beginpage	40
dc.source.endpage	48
dc.source.issue	4
dc.source.journal	IEEE Design & Test
dc.source.volume	32
dc.title	A DfT architecture and tool flow for 3D-SICs with test data compression, embedded cores, and multiple towers
dc.type	Journal article
dspace.entity.type	Publication
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