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3D Stacked Devices and MOT, Innovations for Post-Nanosheet CMOS Scaling

 
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dc.contributor.authorHoriguchi, Naoto
dc.contributor.authorMertens, Hans
dc.contributor.authorChiarella, Thomas
dc.contributor.authorDemuynck, Steven
dc.contributor.authorVega Gonzalez, Victor
dc.contributor.authorVandooren, Anne
dc.contributor.authorVeloso, Anabela
dc.contributor.authorGarcia Bardon, Marie
dc.contributor.authorSisto, Giuliano
dc.contributor.authorGupta, Anshul
dc.contributor.authorTokei, Zsolt
dc.contributor.authorBiesemans, Serge
dc.contributor.authorRyckaert, Julien
dc.date.accessioned2026-05-04T08:38:19Z
dc.date.available2026-05-04T08:38:19Z
dc.date.createdwos2026-03-24
dc.date.issued2023
dc.description.abstract3D stacked devices without area penalty from device-device space, such as complementary FET (CFET), is promising for post-nanosheet CMOS scaling. New MOL architectures, such as backside power delivery network (BSPDN) or Vertical-Horizontal-Vertical routing style, are required to connect 3D stacked devices without wiring congestions and resistance increase. Process/material innovations are necessary to enable high aspect ratio and 3D integration in CFET integration with new MOL architectures.
dc.identifier.doi10.1109/iedm45741.2023.10413701
dc.identifier.issn2380-9248
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/59276
dc.language.isoeng
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherIEEE
dc.source.conferenceInternational Electron Devices Meeting (IEDM)
dc.source.conferencedate2023-12-09
dc.source.conferencelocationSan Francisco
dc.source.journal2023 INTERNATIONAL ELECTRON DEVICES MEETING, IEDM
dc.source.numberofpages4
dc.subject.keywordsPMOS
dc.subject.keywordsNMOS
dc.title

3D Stacked Devices and MOT, Innovations for Post-Nanosheet CMOS Scaling

dc.typeProceedings paper
dspace.entity.typePublication
imec.internal.crawledAt2026-04-07
imec.internal.sourcecrawler
imec.internal.wosCreatedAt2026-04-07
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