Publication:
A scalable neural network emulator with MRAM-based mixed-signal circuits
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.orcid | 0000-0002-2118-596X | |
| cris.virtualsource.department | 64262654-0a4f-467a-91a7-db6ae062fe96 | |
| cris.virtualsource.orcid | 64262654-0a4f-467a-91a7-db6ae062fe96 | |
| dc.contributor.author | Lee, Jua | |
| dc.contributor.author | Song, Jiho | |
| dc.contributor.author | Im, Hyeon Seong | |
| dc.contributor.author | Kim, Jonghwi | |
| dc.contributor.author | Lee, Woonjae | |
| dc.contributor.author | Yi, Wooseok | |
| dc.contributor.author | Kwon, Soonwan | |
| dc.contributor.author | Jung, Byungsu | |
| dc.contributor.author | Kim, Joo Hyoung | |
| dc.contributor.author | Lee, Yoonmyung | |
| dc.contributor.author | Chun, Jung-Hoon | |
| dc.contributor.imecauthor | Kim, Joohyoung | |
| dc.date.accessioned | 2025-06-28T03:55:58Z | |
| dc.date.available | 2025-06-28T03:55:58Z | |
| dc.date.issued | 2025 | |
| dc.description.abstract | In this study, we present a mixed-signal framework that utilizes MRAM (Magneto-resistive Random Access Memory) technology to emulate behaviors observed in biological neural networks on silicon substrates. While modern technology increasingly draws inspiration from biological neural networks, fully understanding these complex systems remains a significant challenge. Our framework integrates multi-bit MRAM synapse arrays and analog circuits to replicate essential neural functions, including Leaky Integrate and Fire (LIF) dynamics, Excitatory and Inhibitory Postsynaptic Potentials (EPSP and IPSP), the refractory period, and the lateral inhibition. A key challenge in using MRAM for neuromorphic systems is its low on/off resistance ratio, which limits the accuracy of current-mode analog computation. To overcome this, we introduce a current subtraction architecture that reliably generates multi-level synaptic currents based on MRAM states. This enables robust analog neural processing while preserving MRAM’s advantages, such as non-volatility and CMOS compatibility. The chip’s adjustable operating frequency allows it to replicate biologically realistic time scales as well as accelerate experimental processes. Experimental results from fabricated chips confirm the successful emulation of biologically inspired neural dynamics, demonstrating the feasibility of MRAM-based analog neuromorphic computation for real-time and scalable neural emulation | |
| dc.description.wosFundingText | The author(s) declare that financial support was received for the research and/or publication of this article. This work was supported in part by the Samsung Electronics, and in part by the Korea Ministry of Trade, Industry, and Energy under the Fostering Global Talents for Innovative Growth Program (P0017312), and in part by the Korea Ministry of Science and Information Technology (No. 2022-0-01171). | |
| dc.identifier.doi | 10.3389/fnins.2025.1599144 | |
| dc.identifier.issn | 2380-8144 | |
| dc.identifier.pmid | MEDLINE:40551852 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/45851 | |
| dc.publisher | FRONTIERS MEDIA SA | |
| dc.source.beginpage | 1 | |
| dc.source.endpage | 17 | |
| dc.source.journal | FRONTIERS IN NEUROSCIENCE | |
| dc.source.numberofpages | 17 | |
| dc.source.volume | 19 | |
| dc.subject.keywords | ON-CHIP | |
| dc.subject.keywords | SYNAPSE | |
| dc.subject.keywords | MEMORY | |
| dc.subject.keywords | SYSTEM | |
| dc.title | A scalable neural network emulator with MRAM-based mixed-signal circuits | |
| dc.type | Journal article | |
| dspace.entity.type | Publication | |
| Files | Original bundle
| |
| Publication available in collections: |