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A scalable neural network emulator with MRAM-based mixed-signal circuits

 
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.orcid0000-0002-2118-596X
cris.virtualsource.department64262654-0a4f-467a-91a7-db6ae062fe96
cris.virtualsource.orcid64262654-0a4f-467a-91a7-db6ae062fe96
dc.contributor.authorLee, Jua
dc.contributor.authorSong, Jiho
dc.contributor.authorIm, Hyeon Seong
dc.contributor.authorKim, Jonghwi
dc.contributor.authorLee, Woonjae
dc.contributor.authorYi, Wooseok
dc.contributor.authorKwon, Soonwan
dc.contributor.authorJung, Byungsu
dc.contributor.authorKim, Joo Hyoung
dc.contributor.authorLee, Yoonmyung
dc.contributor.authorChun, Jung-Hoon
dc.contributor.imecauthorKim, Joohyoung
dc.date.accessioned2025-06-28T03:55:58Z
dc.date.available2025-06-28T03:55:58Z
dc.date.issued2025
dc.description.abstractIn this study, we present a mixed-signal framework that utilizes MRAM (Magneto-resistive Random Access Memory) technology to emulate behaviors observed in biological neural networks on silicon substrates. While modern technology increasingly draws inspiration from biological neural networks, fully understanding these complex systems remains a significant challenge. Our framework integrates multi-bit MRAM synapse arrays and analog circuits to replicate essential neural functions, including Leaky Integrate and Fire (LIF) dynamics, Excitatory and Inhibitory Postsynaptic Potentials (EPSP and IPSP), the refractory period, and the lateral inhibition. A key challenge in using MRAM for neuromorphic systems is its low on/off resistance ratio, which limits the accuracy of current-mode analog computation. To overcome this, we introduce a current subtraction architecture that reliably generates multi-level synaptic currents based on MRAM states. This enables robust analog neural processing while preserving MRAM’s advantages, such as non-volatility and CMOS compatibility. The chip’s adjustable operating frequency allows it to replicate biologically realistic time scales as well as accelerate experimental processes. Experimental results from fabricated chips confirm the successful emulation of biologically inspired neural dynamics, demonstrating the feasibility of MRAM-based analog neuromorphic computation for real-time and scalable neural emulation
dc.description.wosFundingTextThe author(s) declare that financial support was received for the research and/or publication of this article. This work was supported in part by the Samsung Electronics, and in part by the Korea Ministry of Trade, Industry, and Energy under the Fostering Global Talents for Innovative Growth Program (P0017312), and in part by the Korea Ministry of Science and Information Technology (No. 2022-0-01171).
dc.identifier.doi10.3389/fnins.2025.1599144
dc.identifier.issn2380-8144
dc.identifier.pmidMEDLINE:40551852
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/45851
dc.publisherFRONTIERS MEDIA SA
dc.source.beginpage1
dc.source.endpage17
dc.source.journalFRONTIERS IN NEUROSCIENCE
dc.source.numberofpages17
dc.source.volume19
dc.subject.keywordsON-CHIP
dc.subject.keywordsSYNAPSE
dc.subject.keywordsMEMORY
dc.subject.keywordsSYSTEM
dc.title

A scalable neural network emulator with MRAM-based mixed-signal circuits

dc.typeJournal article
dspace.entity.typePublication
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