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Scaling-friendly approaches to minimize the magnitude and asymmetry of wafer warpage during 3-D NAND fabrication

 
dc.contributor.authorOkudur, Oguzhan Orkut
dc.contributor.authorGonzalez, Mario
dc.contributor.authorVan den Bosch, Geert
dc.contributor.authorRosmeulen, Maarten
dc.contributor.imecauthorOkudur, Oguzhan Orkut
dc.contributor.imecauthorGonzalez, Mario
dc.contributor.imecauthorVan den Bosch, Geert
dc.contributor.imecauthorRosmeulen, Maarten
dc.contributor.orcidimecOkudur, Oguzhan Orkut::0000-0002-4790-7772
dc.contributor.orcidimecGonzalez, Mario::0000-0003-4374-4854
dc.contributor.orcidimecVan den Bosch, Geert::0000-0001-9971-6954
dc.contributor.orcidimecRosmeulen, Maarten::0000-0002-3663-7439
dc.date.accessioned2023-08-02T10:06:36Z
dc.date.available2023-06-25T20:34:40Z
dc.date.available2023-07-11T06:35:01Z
dc.date.available2023-08-02T10:06:36Z
dc.date.issued2023
dc.description.wosFundingTextThis work was supported by imec's Industrial Affiliation Program on Storage Memory devices.
dc.identifier.doi10.1016/j.microrel.2023.114996
dc.identifier.issn0026-2714
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/42086
dc.publisherPERGAMON-ELSEVIER SCIENCE LTD
dc.source.beginpageArt. 114996
dc.source.endpagena
dc.source.issueJune
dc.source.journalMICROELECTRONICS RELIABILITY
dc.source.numberofpages9
dc.source.volume145
dc.title

Scaling-friendly approaches to minimize the magnitude and asymmetry of wafer warpage during 3-D NAND fabrication

dc.typeJournal article
dspace.entity.typePublication
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