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Technology/circuit co-optimization and benchmarking for graphene interconnects at sub-10nm technology node

Date

2015
Proceedings Paper
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dc.contributor.authorPan, Chenyun
dc.contributor.authorRaghavan, Praveen
dc.contributor.authorTokei, Zsolt
dc.contributor.authorCatthoor, Francky
dc.contributor.authorNaemi, Azad
dc.contributor.imecauthorTokei, Zsolt
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.date.accessioned2021-10-22T21:37:52Z
dc.date.available2021-10-22T21:37:52Z
dc.date.embargo9999-12-31
dc.date.issued2015
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/25730
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7085495
dc.source.beginpage599
dc.source.conference16th International Symposium on Quality Electronic Design - ISQED
dc.source.conferencedate2/03/2015
dc.source.conferencelocationSanta Clara, CA USA
dc.source.endpage603
dc.title

Technology/circuit co-optimization and benchmarking for graphene interconnects at sub-10nm technology node

dc.typeProceedings paper
dspace.entity.typePublication
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