Publication:
3D metrology and inspection to enable the rise of stacked transistors, wafers and chips
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| cris.virtualsource.orcid | 1a7e9c29-18e0-41f0-a7ca-403c8d63aeb4 | |
| dc.contributor.author | Bogdanowicz, Janusz | |
| dc.contributor.author | Charley, Anne-Laure | |
| dc.contributor.author | Leray, Philippe | |
| dc.contributor.author | Liu, Ru-Gun | |
| dc.contributor.imecauthor | Bogdanowicz, J. | |
| dc.contributor.imecauthor | Charley, A. -L. | |
| dc.contributor.imecauthor | Leray, P. | |
| dc.contributor.imecauthor | Liu, R. G. | |
| dc.date.accessioned | 2025-07-28T03:57:29Z | |
| dc.date.available | 2025-07-28T03:57:29Z | |
| dc.date.issued | 2025 | |
| dc.description.wosFundingText | This work has been enabled in part by the NanoIC pilot line. The acquisition and operation are jointly funded by the Chips Joint Undertaking, through the European Union's Digital Europe (101183266) and Horizon Europe programs (101183277), as well as by the participating states Belgium (Flanders), France, Germany, Finland, Ireland and Romania. For more information, visit nanoic-project.eu. | |
| dc.identifier.doi | 10.1117/12.3052399 | |
| dc.identifier.eisbn | 978-1-5106-8639-7 | |
| dc.identifier.isbn | 978-1-5106-8638-0 | |
| dc.identifier.issn | 0277-786X | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/45958 | |
| dc.publisher | SPIE-INT SOC OPTICAL ENGINEERING | |
| dc.source.beginpage | 1342604-2 | |
| dc.source.conference | 2025 Conference on Metrology Inspection and Process Control-Annual | |
| dc.source.conferencedate | 2025-02-24 | |
| dc.source.conferencelocation | San Jose | |
| dc.source.journal | Proceedings of SPIE | |
| dc.source.numberofpages | 1342604-8 | |
| dc.title | 3D metrology and inspection to enable the rise of stacked transistors, wafers and chips | |
| dc.type | Proceedings paper | |
| dspace.entity.type | Publication | |
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