Sweeping for Leakage in Masked Circuit Layouts

dc.contributor.author	Sijacic, Danilo
dc.contributor.author	Balasch, Josep
dc.contributor.author	Verbauwhede, Ingrid
dc.contributor.imecauthor	Sijacic, Danilo
dc.contributor.imecauthor	Balasch, Josep
dc.contributor.imecauthor	Verbauwhede, Ingrid
dc.contributor.orcidimec	Verbauwhede, Ingrid::0000-0002-0879-076X
dc.date.accessioned	2021-11-10T10:30:44Z
dc.date.available	2021-11-02T16:05:23Z
dc.date.available	2021-11-10T10:30:44Z
dc.date.issued	2020
dc.identifier.eisbn	978-3-9819263-4-7
dc.identifier.issn	1530-1591
dc.identifier.uri	https://imec-publications.be/handle/20.500.12860/38207
dc.publisher	IEEE
dc.source.beginpage	915
dc.source.conference	Design, Automation and Test in Europe Conference and Exhibition (DATE)
dc.source.conferencedate	MAR 09-13, 2020
dc.source.conferencelocation	Grenoble
dc.source.endpage	920
dc.source.journal	Design, Automation and Test in Europe Conference and Exhibition (DATE)
dc.source.numberofpages	6
dc.title	Sweeping for Leakage in Masked Circuit Layouts
dc.type	Proceedings paper
dspace.entity.type	Publication
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