Publication:
Gate Stack Development for Next Gen High Voltage Periphery DRAM Devices
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| dc.contributor.author | Bastos, Joao | |
| dc.contributor.author | Franco, Jacopo | |
| dc.contributor.author | O'Sullivan, Barry | |
| dc.contributor.author | Higashi, Yusuke | |
| dc.contributor.author | Vaisman Chasin, Adrian | |
| dc.contributor.author | Ganguly, Jishnu | |
| dc.contributor.author | Arimura, Hiroaki | |
| dc.contributor.author | Spessot, Alessio | |
| dc.contributor.author | Kim, Min-Soo | |
| dc.contributor.author | Horiguchi, Naoto | |
| dc.date.accessioned | 2026-04-30T13:46:38Z | |
| dc.date.available | 2026-04-30T13:46:38Z | |
| dc.date.createdwos | 2025-10-19 | |
| dc.date.issued | 2025 | |
| dc.description.abstract | Performance enhancement of DRAM memory will eventually require a switch of periphery transistors from planar to finFET configuration. In this work we explore gate-stack options for thick oxide (high-voltage) transistors of DRAM periphery compatible with finFET architecture. We investigate different thick oxide interface layer processes, gate stacks and processing steps and their impact on NBTI, VFB and EOT. A defect-centered analysis enables the correlated interpretation of the trends of these electrical metrics. | |
| dc.description.wosFundingText | This work is supported by imec's industrial affiliation program (IIAP). The authors would also like to acknowledge the support of imec's fab, line and hardware teams. | |
| dc.identifier.doi | 10.1109/irps48204.2025.10982743 | |
| dc.identifier.isbn | 979-8-3315-0478-6 | |
| dc.identifier.issn | 1541-7026 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/59253 | |
| dc.language.iso | eng | |
| dc.provenance.editstepuser | greet.vanhoof@imec.be | |
| dc.publisher | IEEE | |
| dc.source.conference | IEEE International Reliability Physics Symposium (IRPS) | |
| dc.source.conferencedate | 2025-03-30 | |
| dc.source.conferencelocation | Monterey | |
| dc.source.journal | 2025 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, IRPS | |
| dc.source.numberofpages | 8 | |
| dc.subject.keywords | TEMPERATURE | |
| dc.subject.keywords | OXIDATION | |
| dc.title | Gate Stack Development for Next Gen High Voltage Periphery DRAM Devices | |
| dc.type | Proceedings paper | |
| dspace.entity.type | Publication | |
| imec.internal.crawledAt | 2026-04-07 | |
| imec.internal.source | crawler | |
| imec.internal.wosCreatedAt | 2026-04-07 | |
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