Publication:

Microarchitectural Exploration of STT-MRAM Last-level Cache Parameters for Energy-efficient Devices

Date

2022
Journal article
https://doi.org/10.1145/3490391
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dc.contributor.authorMarinelli, Tommaso
dc.contributor.authorGomez Perez, Jignacio
dc.contributor.authorTenllado, Christian
dc.contributor.authorKomalan, Manu
dc.contributor.authorGupta, Mohit
dc.contributor.authorCatthoor, Francky
dc.contributor.imecauthorKomalan, Manu
dc.contributor.imecauthorGupta, Mohit
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidextMarinelli, Tommaso::0000-0002-8555-3581
dc.contributor.orcidextTenllado, Christian::0000-0003-2348-4741
dc.contributor.orcidimecKomalan, Manu::0000-0002-0029-6548
dc.contributor.orcidimecGupta, Mohit::0000-0002-1924-1264
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.date.accessioned2023-06-29T14:21:38Z
dc.date.available2023-06-20T10:35:21Z
dc.date.available2023-06-29T07:31:55Z
dc.date.available2023-06-29T14:21:38Z
dc.date.embargo2022-01-14
dc.date.issued2022
dc.description.wosFundingTextThis work has been supported by the European Commission (Regional Development Fund), the Spanish Ministry of Science and Innovation, and the Community of Madrid, under grants RTI2018-093684-B-I00 and S2018/TCS-4423.
dc.identifier.doi10.1145/3490391
dc.identifier.issn1539-9087
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/41883
dc.publisherASSOC COMPUTING MACHINERY
dc.source.beginpageArt. 3
dc.source.endpagena
dc.source.issue1
dc.source.journalACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS
dc.source.numberofpages20
dc.source.volume21
dc.subject.keywordsRAM
dc.subject.keywordsPERFORMANCE
dc.subject.keywordsDESIGN
dc.subject.keywordsSTT-MRAM, LLC
dc.title

Microarchitectural Exploration of STT-MRAM Last-level Cache Parameters for Energy-efficient Devices

dc.typeJournal article
dspace.entity.typePublication
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