Investigation of Cryogenic Aging in 28 nm CMOS: Suppression of BTI and HCD in Circuits and SRAM

Abstract

The increasing interest in cryogenic circuits is driven by their transformative potential across high-performance computing, medical devices, space exploration, and quantum technologies. Operating transistors at cryogenic temperatures, such as 77 K and below, yields substantial improvements, including increased ON current, reduced OFF current, and enhanced sub-threshold slope, paving the way for significant gains in efficiency. While recent studies have explored device-level reliability at cryogenic temperatures, circuit-level reliability-particularly under bias temperature instability (BTI) and hot carrier degradation (HCD)-remains underexamined, leaving critical aging mechanisms at these temperatures poorly understood. To bridge this gap, we designed and fabricated a fully customized chip in a commercial 28 nm technology. The chip integrates diverse ring oscillator (RO) circuits for precise characterization of BTI and HCD aging effects, enabling evaluation of their impact on performance at cryogenic temperatures as low as 4 K. This work ensures that as cryogenic CMOS technologies drive innovation in critical applications, their reliability is comprehensively understood and advanced.