Publication:

Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC

Date

2025
Journal article
https://doi.org/10.1109/TVLSI.2024.3467148
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dc.contributor.authorDas, Sudipta
dc.contributor.authorRiedel, Samuel
dc.contributor.authorNaeim, Mohamed
dc.contributor.authorBrunion, Moritz
dc.contributor.authorBertuletti, Marco
dc.contributor.authorBenini, Luca
dc.contributor.authorRyckaert, Julien
dc.contributor.authorMyers, James
dc.contributor.authorBiswas, Dwaipayan
dc.contributor.authorMilojevic, Dragomir
dc.contributor.imecauthorDas, Sudipta
dc.contributor.imecauthorNaeim, Mohamed
dc.contributor.imecauthorBrunion, Moritz
dc.contributor.imecauthorRyckaert, Julien
dc.contributor.imecauthorMyers, James
dc.contributor.imecauthorBiswas, Dwaipayan
dc.contributor.imecauthorMilojevic, Dragomir
dc.contributor.orcidimecDas, Sudipta::0009-0007-2998-9827
dc.contributor.orcidimecBrunion, Moritz::0000-0001-7842-7774
dc.contributor.orcidimecBiswas, Dwaipayan::0000-0002-1087-3433
dc.date.accessioned2025-05-05T12:39:55Z
dc.date.available2024-10-30T17:13:36Z
dc.date.available2025-05-05T12:39:55Z
dc.date.issued2025
dc.identifier.doi10.1109/TVLSI.2024.3467148
dc.identifier.issn1063-8210
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/44699
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.source.beginpage346
dc.source.endpage357
dc.source.issue2
dc.source.journalIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
dc.source.numberofpages12
dc.source.volume33
dc.subject.keywordsMEMORY
dc.subject.keywordsSYSTEM
dc.subject.keywordsDESIGN
dc.title

Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC

dc.typeJournal article
dspace.entity.typePublication
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