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DfT architecture and ATPG for interconnect tests of JEDEC wide-IO DRAM memory-on-Logic 2.5D/3D-stacks
Publication:
DfT architecture and ATPG for interconnect tests of JEDEC wide-IO DRAM memory-on-Logic 2.5D/3D-stacks
Date
2012-05
Proceedings Paper
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Deutsch, Sergej
;
Chickermane, Vivek
;
Keller, Brion
;
Mukherjee, Subhasish
;
Sood, Navdeep
;
Marinissen, Erik Jan
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1926
since deposited on 2021-10-20
Acq. date: 2025-10-23
Citations
Metrics
Views
1926
since deposited on 2021-10-20
Acq. date: 2025-10-23
Citations