Publication:

Double-gate Si junction-less n-type transistor for high performance Cu-BEOL compatible applications using 3D sequential integration

Date

2017
Proceedings Paper
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dc.contributor.authorVandooren, Anne
dc.contributor.authorWitters, Liesbeth
dc.contributor.authorVecchio, Emma
dc.contributor.authorKunnen, Eddy
dc.contributor.authorHellings, Geert
dc.contributor.authorPeng, Lan
dc.contributor.authorInoue, Fumihiro
dc.contributor.authorLi, Waikin
dc.contributor.authorWaldron, Niamh
dc.contributor.authorMocuta, Dan
dc.contributor.authorCollaert, Nadine
dc.contributor.imecauthorVandooren, Anne
dc.contributor.imecauthorWitters, Liesbeth
dc.contributor.imecauthorVecchio, Emma
dc.contributor.imecauthorHellings, Geert
dc.contributor.imecauthorPeng, Lan
dc.contributor.imecauthorInoue, Fumihiro
dc.contributor.imecauthorLi, Waikin
dc.contributor.imecauthorWaldron, Niamh
dc.contributor.imecauthorCollaert, Nadine
dc.contributor.orcidimecVandooren, Anne::0000-0002-2412-0176
dc.contributor.orcidimecHellings, Geert::0000-0002-5376-2119
dc.contributor.orcidimecPeng, Lan::0000-0003-1824-126X
dc.contributor.orcidimecCollaert, Nadine::0000-0002-8062-3165
dc.date.accessioned2021-10-24T17:06:31Z
dc.date.available2021-10-24T17:06:31Z
dc.date.embargo9999-12-31
dc.date.issued2017
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/29773
dc.identifier.urlhttp://ieeexplore.ieee.org/document/8309234/
dc.source.beginpage5.3
dc.source.conferenceIEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference - IEEE S3S
dc.source.conferencedate16/10/2017
dc.source.conferencelocationBurlingame, CA USA
dc.title

Double-gate Si junction-less n-type transistor for high performance Cu-BEOL compatible applications using 3D sequential integration

dc.typeProceedings paper
dspace.entity.typePublication
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