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A Novel Design Reversible logic based Configurable Fault-Tolerant Embryonic Hardware

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dc.contributor.authorKhalil, Kasem
dc.contributor.authorDey, Bappaditya
dc.contributor.authorSherazi, Yasser
dc.contributor.authorKumar, Ashok
dc.contributor.authorBayoumi, Magdy
dc.contributor.imecauthorDey, Bappaditya
dc.contributor.imecauthorSherazi, Yasser
dc.contributor.orcidimecDey, Bappaditya::0000-0002-0886-137X
dc.date.accessioned2022-01-25T09:43:11Z
dc.date.available2021-11-11T03:04:05Z
dc.date.available2022-01-25T09:38:31Z
dc.date.available2022-01-25T09:43:11Z
dc.date.issued2020
dc.identifier.eisbn978-1-7281-3320-1
dc.identifier.issn0271-4302
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/38418
dc.publisherIEEE
dc.source.conferenceIEEE International Symposium on Circuits and Systems (ISCAS)
dc.source.conferencedateOCT 10-21, 2020
dc.source.conferencelocationVirtual
dc.source.journalna
dc.source.numberofpages5
dc.title

A Novel Design Reversible logic based Configurable Fault-Tolerant Embryonic Hardware

dc.typeProceedings paper
dspace.entity.typePublication
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