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Threshold voltage design incompatibility between partially-depleted SOI and bulk CMOS transistors

Date

1999
Proceedings Paper
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dc.contributor.authorvan Meer, Hans
dc.contributor.authorLyu, Jeong-ho
dc.contributor.authorKubicek, Stefan
dc.contributor.authorGeenen, Luc
dc.contributor.authorDe Meyer, Kristin
dc.contributor.imecauthorKubicek, Stefan
dc.contributor.imecauthorDe Meyer, Kristin
dc.date.accessioned2021-10-14T11:48:29Z
dc.date.available2021-10-14T11:48:29Z
dc.date.issued1999
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/3939
dc.source.beginpage32
dc.source.conferenceProceedings of the IEEE SOI Conference; October 1999; Rohnert Parc, Ca, USA.
dc.source.conferencelocation
dc.source.endpage33
dc.title

Threshold voltage design incompatibility between partially-depleted SOI and bulk CMOS transistors

dc.typeProceedings paper
dspace.entity.typePublication
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