Publication:

Layer and Stacking Effects on Transport Properties in Steep-Slope Cold-Metal-Source FETs

 
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
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cris.virtual.orcid0000-0002-4157-1956
cris.virtual.orcid0009-0007-1972-338X
cris.virtual.orcid0000-0002-5260-0281
cris.virtualsource.departmentf9b525b6-66d0-4e40-8dd4-46fc733e347c
cris.virtualsource.department69351920-36ea-45bc-9073-c081202aefde
cris.virtualsource.department7e65e670-a519-4d5e-82e5-8931848f4edc
cris.virtualsource.orcidf9b525b6-66d0-4e40-8dd4-46fc733e347c
cris.virtualsource.orcid69351920-36ea-45bc-9073-c081202aefde
cris.virtualsource.orcid7e65e670-a519-4d5e-82e5-8931848f4edc
dc.contributor.authorChang, Chiao-Yu
dc.contributor.authorSoree, Bart
dc.contributor.authorAfzalian, Aryan
dc.date.accessioned2026-09-14T11:15:29Z
dc.date.available2026-09-14T11:15:29Z
dc.date.createdwos2026
dc.date.issued2025
dc.description.abstractWe investigate the impacts of layer number and heterostructure stacking on the transport of 2D cold-metal-source FETs within the DFT-NEGF framework using our NEGF solver, ATOMOS, which enables electron-phonon coupling analysis. Our simulations demonstrate that optimized NbS2/WS2 stacking reduces the van der Waals gap, enhancing on-current, while additional cold-metal layers introduce density of states near the Fermi level, further improving the on-current. This study presents an effective design strategy for cold-source materials and contacts to achieve steep-slope transport.
dc.description.wosFundingTextThis work has received funding from the European Commission-EU Attoswitch project under grant agreement n. 101135571.
dc.identifier.doi10.1109/sispad66650.2025.11186390
dc.identifier.isbn979-8-3315-4884-1
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/60340
dc.language.isoeng
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherIEEE
dc.source.beginpage1
dc.source.conferenceInternational Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
dc.source.conferencedate2025-09-24
dc.source.conferencelocationGrenoble
dc.source.endpage4
dc.source.journal2025 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES, SISPAD
dc.source.numberofpages4
dc.title

Layer and Stacking Effects on Transport Properties in Steep-Slope Cold-Metal-Source FETs

dc.typeProceedings paper
dspace.entity.typePublication
imec.internal.crawledAt2025-10-22
imec.internal.sourcecrawler
imec.internal.wosCreatedAt2026-09-13
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