Publication:

Process challenges in 0-level packaging using 100μm thin chip capping with TSV

Date

2012
Proceedings Paper
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dc.contributor.authorPham, Nga
dc.contributor.authorCherman, Vladimir
dc.contributor.authorTutunjyan, Nina
dc.contributor.authorTeugels, Lieve
dc.contributor.authorSabuncuoglu Tezcan, Deniz
dc.contributor.authorTilmans, Harrie
dc.contributor.imecauthorPham, Nga
dc.contributor.imecauthorCherman, Vladimir
dc.contributor.imecauthorTutunjyan, Nina
dc.contributor.imecauthorTeugels, Lieve
dc.contributor.imecauthorSabuncuoglu Tezcan, Deniz
dc.contributor.imecauthorTilmans, Harrie
dc.contributor.orcidimecTeugels, Lieve::0000-0002-6613-9414
dc.contributor.orcidimecSabuncuoglu Tezcan, Deniz::0000-0002-9237-7862
dc.contributor.orcidimecTilmans, Harrie::0000-0003-4240-4962
dc.contributor.orcidimecCherman, Vladimir::0000-0002-8068-9236
dc.date.accessioned2021-10-20T14:32:50Z
dc.date.available2021-10-20T14:32:50Z
dc.date.embargo9999-12-31
dc.date.issued2012
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/21297
dc.source.beginpage276
dc.source.conference45th International Symposium on Microelectronics - IMAPS
dc.source.conferencedate9/09/2012
dc.source.conferencelocationSan Diego, CA USA
dc.source.endpage282
dc.title

Process challenges in 0-level packaging using 100μm thin chip capping with TSV

dc.typeProceedings paper
dspace.entity.typePublication
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