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A 50nm high-k poly silicon gate stack with a buried SiGe channel
Publication:
A 50nm high-k poly silicon gate stack with a buried SiGe channel
Date
2007
Proceedings Paper
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Basic data
APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Jakschik, S.
;
Hoffmann, Thomas Y.
;
Cho, Hag-Ju
;
Veloso, Anabela
;
Loo, Roger
;
Hyun, S.
;
Sorada, H.
;
Inoue, A.
;
de Potter de ten Broeck, Muriel
;
Eneman, Geert
;
Severi, Simone
;
Absil, Philippe
;
Biesemans, Serge
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2029
since deposited on 2021-10-16
Acq. date: 2025-10-23
Citations
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Views
2029
since deposited on 2021-10-16
Acq. date: 2025-10-23
Citations