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A Reversible-Logic based Architecture for VGGNet

 
dc.contributor.authorDey, Bappaditya
dc.contributor.authorKhalil, Kasem
dc.contributor.authorKumar, Ashok
dc.contributor.authorBayoumi, Magdy
dc.contributor.imecauthorDey, Bappaditya
dc.contributor.orcidimecDey, Bappaditya::0000-0002-0886-137X
dc.date.accessioned2022-08-23T10:23:35Z
dc.date.available2022-05-05T02:17:49Z
dc.date.available2022-07-08T09:34:01Z
dc.date.available2022-08-23T10:23:35Z
dc.date.issued2021
dc.identifier.doi10.1109/ICECS53924.2021.9665605
dc.identifier.eisbn978-1-7281-8281-0
dc.identifier.isbn978-1-7281-8281-0
dc.identifier.issn978-1-7281-9493-6
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/39755
dc.publisherIEEE
dc.source.conference28th IEEE International Conference on Electronics, Circuits, and Systems (IEEE ICECS)
dc.source.conferencedateNOV 28-DEC 01, 2021
dc.source.conferencelocationDubai
dc.source.journal2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)
dc.source.numberofpages4
dc.title

A Reversible-Logic based Architecture for VGGNet

dc.typeProceedings paper
dspace.entity.typePublication
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