Publication:

Advanced FinFET devices for sub-32nm technology nodes: characteristics and integration challenges

Date

2009
Proceedings Paper
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dc.contributor.authorVeloso, Anabela
dc.contributor.authorCollaert, Nadine
dc.contributor.authorDe Keersgieter, An
dc.contributor.authorWitters, Liesbeth
dc.contributor.authorRooyackers, Rita
dc.contributor.authorVan Dal, Mark
dc.contributor.authorDuffy, Ray
dc.contributor.authorPawlak, Bartek
dc.contributor.authorLander, Rob
dc.contributor.authorHoffmann, Thomas Y.
dc.contributor.imecauthorVeloso, Anabela
dc.contributor.imecauthorCollaert, Nadine
dc.contributor.imecauthorDe Keersgieter, An
dc.contributor.imecauthorWitters, Liesbeth
dc.contributor.imecauthorVan Dal, Mark
dc.contributor.imecauthorPawlak, Bartek
dc.contributor.orcidimecCollaert, Nadine::0000-0002-8062-3165
dc.contributor.orcidimecDe Keersgieter, An::0000-0002-5527-8582
dc.date.accessioned2021-10-18T04:37:25Z
dc.date.available2021-10-18T04:37:25Z
dc.date.embargo9999-12-31
dc.date.issued2009
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/16453
dc.source.beginpage45
dc.source.conferenceSilicon-on-Insulator Technology and Devices 14
dc.source.conferencedate24/05/2009
dc.source.conferencelocationSan Francisco, CA USA
dc.source.endpage54
dc.title

Advanced FinFET devices for sub-32nm technology nodes: characteristics and integration challenges

dc.typeProceedings paper
dspace.entity.typePublication
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