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Scaling CMOS: finding the optimal gate dielectric

Date

2004-03
Proceedings Paper
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dc.contributor.authorKauerauf, Thomas
dc.contributor.authorGovoreanu, Bogdan
dc.contributor.authorDegraeve, Robin
dc.contributor.authorGroeseneken, Guido
dc.contributor.imecauthorGovoreanu, Bogdan
dc.contributor.imecauthorDegraeve, Robin
dc.contributor.imecauthorGroeseneken, Guido
dc.date.accessioned2021-10-15T14:07:25Z
dc.date.available2021-10-15T14:07:25Z
dc.date.embargo9999-12-31
dc.date.issued2004-03
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/9113
dc.source.beginpage35
dc.source.conferenceULIS - 5th European Workshop on ULtimate Integration of Silicon
dc.source.conferencedate11/03/2004
dc.source.conferencelocationLeuven Belgium
dc.source.endpage38
dc.title

Scaling CMOS: finding the optimal gate dielectric

dc.typeProceedings paper
dspace.entity.typePublication
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