2025 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, IITC
Abstract
This study investigates the overlay performance of a 2-level Ru semi-damascene integration using a Spacer-is-Dielectric (SID) SADP strategy to create 18 nm metal pitch Ru metal lines combined with fully self-aligned vias (FSAV). Furthermore, the impact of via overlay on FSAV electrical performance was experimentally assessed. Results show that ≤ 3 nm lot Mxblock-to-Mx overlay residuals can be achieved using an SID-SADP approach with TiN as hard mask. Moreover, an >80% kelvin via yield could be obtained for a via y-overlay range of 10 nm and via x-overlay range of 11 nm, highlighting the FSAV process’s robustness for future interconnect scaling.
