Publication:

In-line metrology and inspection for hidden structure of lateral gate-all-around devices enabled by high voltage critical dimension scanning electron microscopy

 
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.orcid0000-0003-3498-5082
cris.virtual.orcid0000-0001-5490-0416
cris.virtual.orcid0000-0002-7503-8922
cris.virtual.orcid0000-0002-8297-5076
cris.virtual.orcid0000-0003-4745-0167
cris.virtual.orcid0000-0002-3392-6892
cris.virtualsource.department0cddeaa4-4a9c-44ee-a5d6-ba4f3945e8a7
cris.virtualsource.department9f04b13f-f81c-4d48-a5bd-0b2cb5210392
cris.virtualsource.department9a3d60e7-3e8b-4366-b479-ea599b23d28b
cris.virtualsource.departmentbf23291b-8cd7-495b-b210-564de11c9d4f
cris.virtualsource.department264c186e-7bc4-4bed-8d4f-11fe1bff9e26
cris.virtualsource.department49b2e4a0-e3c7-4524-b945-f94059646804
cris.virtualsource.orcid0cddeaa4-4a9c-44ee-a5d6-ba4f3945e8a7
cris.virtualsource.orcid9f04b13f-f81c-4d48-a5bd-0b2cb5210392
cris.virtualsource.orcid9a3d60e7-3e8b-4366-b479-ea599b23d28b
cris.virtualsource.orcidbf23291b-8cd7-495b-b210-564de11c9d4f
cris.virtualsource.orcid264c186e-7bc4-4bed-8d4f-11fe1bff9e26
cris.virtualsource.orcid49b2e4a0-e3c7-4524-b945-f94059646804
dc.contributor.authorShohjoh, Tomoyasu
dc.contributor.authorIsawa, Miki
dc.contributor.authorLorusso, Gian
dc.contributor.authorHoriguchi, Naoto
dc.contributor.authorMertens, Hans
dc.contributor.authorBogdanowicz, Janusz
dc.contributor.authorDe Bisschop, Peter
dc.contributor.authorCharley, Anne-Laure
dc.date.accessioned2026-07-27T11:51:43Z
dc.date.available2026-07-27T11:51:43Z
dc.date.createdwos2026
dc.date.issued2026
dc.description.abstractBackground Lateral gate-all-around (LGAA) device architectures—including nanosheet and forksheet structures—are becoming the dominant transistor platforms for sub-3 nm technology nodes. These architectures introduce multiple buried features such as silicon-germanium (SiGe) layers, dielectric-wall voids, and channel-release interfaces, many of which lie beneath hard-mask or dummy-gate stacks in actual process flows. As a result, the need for subsurface metrology that can access these features prior to or without cross-sectioning has grown substantially. Aim The aim is to isolate and evaluate the intrinsic subsurface-visibility capability of high-voltage critical-dimension scanning electron microscopy (HV CD-SEM). This study investigates its feasibility using nanosheet test structures intentionally prepared without upper hard-mask or dummy-gate layers. Approach Three LGAA-relevant inspection targets were examined: (1) voids within dielectric walls, (2) SiGe lateral recess amounts, and (3) multilayer SiGe residues after channel release. HV CD-SEM images were acquired at elevated landing energies to enhance backscattered-electron (BSE) sensitivity to embedded features. Monte Carlo simulations were performed to interpret voltage-dependent BSE signatures, and selected features were verified by transmission electron microscopy (TEM) or energy-dispersive X-ray spectroscopy (EDX). Results HV CD-SEM successfully visualized dielectric-wall voids, extracted SiGe recess amounts using SE/BSE paired contrast, and detected SiGe residues originating from distinct depths within the nanosheet stack. Recess extraction was applied at 163 sampling locations, enabling wafer-level evaluation of layout-dependent micro-loading effects, whereas TEM cross-sections provided limited but essential reference values. Simulations correctly predicted the voltage-dependent detectability of multilayer SiGe residues, and EDX confirmed Ge-related contrast in the HV CD-SEM images. Conclusions These results show that HV CD-SEM possesses intrinsic subsurface-visibility capability when upper hard-mask and dummy-gate layers are absent, demonstrating feasibility for detecting voids, SiGe recess profiles, and multilayer SiGe residues in nanosheet structures. Extending this approach to fully processed LGAA devices—where upper gate-stack layers remain in place—represents an essentially next step toward establishing HV CD-SEM as a comprehensive inline subsurface metrology technique.
dc.description.wosFundingTextThe authors would like to thank all the members of the imec-Hitachi JDP from imec and Hitachi High-Tech for their insightful suggestions and discussions.
dc.identifier.doi10.1117/1.jmm.25.1.014002
dc.identifier.eissn2708-8340
dc.identifier.issn2708-8340
dc.identifier.issn1932-5150
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/59987
dc.language.isoeng
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherSPIE-SOC PHOTO-OPTICAL INSTRUMENTATION ENGINEERS
dc.source.beginpage014002
dc.source.issue1
dc.source.journalJOURNAL OF MICRO-NANOPATTERNING MATERIALS AND METROLOGY-JM3
dc.source.numberofpages13
dc.source.volume25
dc.title

In-line metrology and inspection for hidden structure of lateral gate-all-around devices enabled by high voltage critical dimension scanning electron microscopy

dc.typeJournal article
dspace.entity.typePublication
imec.internal.crawledAt2026-03-05
imec.internal.sourcecrawler
imec.internal.wosCreatedAt2026-07-14
Files
Publication available in collections: