Publication:

Gate-all-around transistors based on vertically stacked Si nanowires: recent progress in CMOS integration and in advanced inline metrology

Date

2018
Proceedings Paper
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dc.contributor.authorMertens, Hans
dc.contributor.authorRitzenthaler, Romain
dc.contributor.authorMocuta, Dan
dc.contributor.authorHoriguchi, Naoto
dc.contributor.imecauthorMertens, Hans
dc.contributor.imecauthorRitzenthaler, Romain
dc.contributor.imecauthorHoriguchi, Naoto
dc.contributor.orcidimecRitzenthaler, Romain::0000-0002-8615-3272
dc.contributor.orcidimecHoriguchi, Naoto::0000-0001-5490-0416
dc.date.accessioned2021-10-25T23:24:50Z
dc.date.available2021-10-25T23:24:50Z
dc.date.embargo9999-12-31
dc.date.issued2018
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/31337
dc.source.beginpage155
dc.source.conference50th International Conference on Solid State Devices and Materials - SSDM
dc.source.conferencedate9/09/2018
dc.source.conferencelocationTokyo Japan
dc.source.endpage156
dc.title

Gate-all-around transistors based on vertically stacked Si nanowires: recent progress in CMOS integration and in advanced inline metrology

dc.typeProceedings paper
dspace.entity.typePublication
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