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Back gate voltage influence on the LDD SOI NMOSFET series resistance extraction from 150 to 300 K

Date

2000
Proceedings Paper
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dc.contributor.authorNicolett, A. S.
dc.contributor.authorMartino, Joao Antonio
dc.contributor.authorSimoen, Eddy
dc.contributor.authorClaeys, C.
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.date.accessioned2021-10-14T13:27:44Z
dc.date.available2021-10-14T13:27:44Z
dc.date.embargo9999-12-31
dc.date.issued2000
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/4617
dc.source.beginpage187
dc.source.conferencePerspectives, Sciences and Technologies of Novel Silicon-on-Insulator Devices
dc.source.conferencedate12/10/1998
dc.source.conferencelocationKiev Ukraine
dc.source.endpage193
dc.title

Back gate voltage influence on the LDD SOI NMOSFET series resistance extraction from 150 to 300 K

dc.typeProceedings paper
dspace.entity.typePublication
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